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5555 n.e. moore ct. ? hillsboro, oregon 97124 - 6421 ? phone (503) 268 - 8000 ? fax (503) 268 - 8347 internet: http://www.latticesemi.com gal ? 22 v 10 device datasheet september 2010 all devices discontinued! product change notifications (pcns) have been issued to discontinue all devices in this data sheet. the original datasheet pages have not been modified and do not reflect those cha nges. please refer to the table below for reference pcn and current product status . product line ordering part number product status reference pcn gal22v10d gal22v10d - 7lp discontinued pcn#09 - 10 gal22v10d - 7lpn gal22v10d - 10lp pcn#1 3 - 10 gal22v10d - 10lpn gal22v10d - 15lp gal22v10d - 15lpn gal22v10d - 25lp gal22v10d - 25lpn gal22v10d - 7lpi pcn#09 - 10 gal22v10d - 7lpni gal22v10d - 10lpi pcn#1 3 - 10 gal22v10d - 10lpni gal22v10d - 15lpi gal22v10d - 15lpni gal22v10d - 20lpi gal22v10d - 20lpni gal22v10d - 25lpi gal22v10d - 25lpni gal22v10d - 10qp gal2 2v10d - 10qpn gal22v10d - 15qp gal22v10d - 15qpn gal22v10d - 25qp gal22v10d - 25qpn gal22v10d - 10ls pcn#06 - 07 gal22v10d - 15ls gal22v10d - 25ls gal22v10d - 4lj pcn#09 - 10 gal22v10d - 4ljn gal22v10d - 5lj pcn#1 3 - 10 gal22v10d - 5ljn
5555 n.e. moore ct. ? hillsboro, oregon 97124 - 6421 ? phone (503) 268 - 8000 ? fax (503) 268 - 8347 internet: http://www.latticesemi.com product line ordering part number product status reference pcn gal22v10d (contd) g al22v10d - 7lj discontinued pcn#1 3 - 10 gal22v10d - 7ljn gal22v10d - 10lj gal22v10d - 10ljn gal22v10d - 15lj gal22v10d - 15ljn gal22v10d - 25lj gal22v10d - 25ljn gal22v10d - 7lji pcn#09 - 10 gal22v10d - 7ljni gal22v10d - 10lji gal22v10d - 10ljni gal22v10d - 15lji pcn#1 3 - 10 gal22v10d - 15ljni gal22v10d - 20lji gal22v10d - 20ljni gal22v10d - 25lji gal22v10d - 25ljni gal22v10d - 10qj gal22v10 d - 10qjn gal22v10d - 15qj gal22v10d - 15qjn gal22v10d - 25qj gal22v10d - 25qjn
specifications gal22v10 1 228 nc i/clk i i i i i i i i nc nc nc gnd i i i i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q vcc i/o/q i/o/q i/o/q 42 6 25 19 18 21 23 16 14 12 11 9 7 5 features ? high performance e 2 cmos ? technology ? 4 ns maximum propagation delay ? fmax = 250 mhz ? 3.5 ns maximum from clock input to data output ? ultramos ? advanced cmos technology ? active pull-ups on all pins ? compatible with standard 22v10 devices ? fully function/fuse-map/parametric compatible with bipolar and uvcmos 22v10 devices ? 50% to 75% reduction in power versus bipolar ? 90ma typical icc on low power device ? 45ma typical icc on quarter power device ?e 2 cell technology ? reconfigurable logic ? reprogrammable cells ? 100% tested/100% yields ? high speed electrical erasure (<100ms) ? 20 year data retention ? ten output logic macrocells ? maximum flexibility for complex logic designs ? preload and power-on reset of registers ? 100% functional testability ? applications include: ? dma control ? state machine control ? high speed graphics processing ? standard logic speed upgrade ? electronic signature for identification ? lead-free package options escription description the gal22v10, at 4ns maximum propagation delay time, combines a high performance cmos process with electrically erasable (e 2 ) floating gate technology to provide the highest performance avail- able of any 22v10 device on the market. cmos circuitry allows the gal22v10 to consume much less power when compared to bipolar 22v10 devices. e 2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. the generic architecture provides maximum design flexibility by allowing the output logic macrocell (olmc) to be configured by the user. the gal22v10 is fully function/fuse map/parametric com- patible with standard bipolar and cmos 22v10 devices. unique test circuitry and reprogrammable cells allow complete ac, dc, and functional testing during manufacture. as a result, lat- tice semiconductor delivers 100% field programmability and func- tionality of all gal products. in addition, 100 erase/write cycles and data retention in excess of 20 years are specified. gal22v10 high performance e 2 cmos pld generic array logic? copyright ? 2006 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. december 2006 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com gal22v10 top view plcc 1 12 13 24 i/clk i i i i i i i i i i gnd vcc i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i 6 18 gal 22v10 dip 22v10_12 functional block diagram pin configuration soic gal22v10 top view lead-free package options available! 1 12 13 24 i i i i i i i i i gnd i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i 6 18 i/clk i vcc i/o/q programmable and-array (132x44) i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i i/clk i i i i i i i i i i reset preset 8 10 12 14 16 16 14 12 10 8 olmc olmc olmc olmc olmc olmc olmc olmc olmc olmc all devices discontinued
specifications gal22v10 2 conventional packaging commercial grade specifications industrial grade specifications gal22v10 ordering information )sn(dp t) sn(us t) sn(oc t) am(cc i# gniredr oe gakcap 5. 755 . 40 61 01v22la gdi pl7- pidcitsalpnip-42 5. 45 . 40 61 01v22la gdi jl7- cclpdael-82 0 177 0 61 01v22la gdi pl01- pidcitsalpnip-42 061 01v22la gdi jl01- cclp dael-82 5 10 18 0 3 1g i pl51-d01v22la pidcitsalpnip-42 03 1i jl51-d01v22lag cclpdael-82 0 24 10 10 3 1i pl02-d01v22lag pidcitsalpnip-42 03 1i jl02-d01v22lag cclpdael-82 5 25 15 10 3 1i pl52-d01v22lag pidcitsalpnip-42 03 1i jl52-d01v22lag cclpdael-82 )sn(dp t) sn(us t) sn(oc t) am(cc i# gnired or ge akcap 45 . 25 . 30 4 1j l4-d01v22lag cclpdael-82 534 0 4 1j l5-d01v22lag cclpdael-82 5. 75 . 45 . 40 4 1p l7-d01v22lag pidcitsalpnip-42 5. 45 . 40 4 1j l7-d01v22lag cclpdael-82 0 1775 5p q01- d0 1v22lag pidcitsalpnip-42 5 5j q01-d01v22lag cclpdael-82 90 90 130 90 lp 01-d01v22lag pidcitsalpnip-42 03 1j l01-d01v22lag cclpdael-82 0 3l s 1 01-d01v22lag ciosnip-42 5 10 185 5p q51-d01v22lag pidcitsalpnip-42 5 5j q51-d01v22lag cclpdael-82 lp 51-d01v22lag pidcitsalpnip-42 lj 51-d01v22lag cclpdael-82 ls 1 51-d01v22lag ciosnip-42 5 25 15 15 5p q52-d01v22lag pidcitsalpnip-42 5 5j q52-d01v22lag cclpdael-82 0 9p l52-d01v22lag pidcitsalpnip-42 0 9j l52-d01v22lag cclpdael-82 0 9s 1 l52-d01v22lag ciosnip-42 1. discontinued per pcn #06-07. contact rochester electronics for available inventory. all devices discontinued
specifications gal22v10 3 part number description lead-free packaging commercial grade specifications )sn(dp t) sn(us t) sn(oc t) am(cc i# gniredr oe gakcap 45 . 25 . 30 4 1n jl4-d01v22lag cclpdael-82eerf-dael 534 0 4 1n jl5-d01v22lag cclpdael-82eerf-dael 5. 75 . 45 . 40 4 1n pl7-d01v22lag pidcitsalpnip-42eerf-dael 5. 45 . 40 4 1n jl7-d01v22lag cclpdael-82eerf-dael 0 1775 5n pq01 -d01v22lag pidcitsalpnip-42eerf-dael 5 5n jq01-d01v22lag cclpdael-82eerf-dael 03 1n pl01-d01v22lag pidcitsalpnip-42eerf-dael 03 1n jl01-d01v22lag cclpdael-82eerf-dael 5 10 185 5n pq51- d01v22lag pidcitsalpnip-42eerf-dael 5 5n jq51-d01v22lag cclpdael-82eerf-dael 0 9n pl51-d01v22lag pidcitsalpnip-42eerf-dael 0 9n jl51-d01v22lag cclpdael-82eerf-dael 5 25 15 15 5n pq52-d01v22lag pidcitsalpnip-42eerf-dael 5 5n jq52-d01v22lag cclpdael-82eerf-dael 0 9n pl52-d01v22lag pidcitsalpnip-42eerf-dael 0 9n jl52-d01v22lag cclpdael-82eerf-dael industrial grade specifications )sn(dp t) sn(us t) sn(oc t) am(cc i# gniredr oe gakcap 5. 755 . 40 6 1i npl7-d01v22lag pidcitsalpnip-42eerf-dael 5. 45 . 40 6 1i njl7-d01v22lag cclpdael-82eerf-dael 0 177 0 6 1i npl01-d01v22lag pidcitsalpnip-42eerf-dael 06 1i njl01-d01v22lag cclpdael-82eerf-dael 5 10 18 0 3 1i npl51 -d01v22lag pidcitsalpnip-42eerf-dael 03 1i njl51-d01v22lag cclpdael-82eerf-dael 0 24 10 10 3 1i npl02-d01v22lag pidcitsalpnip-42eerf-dael 03 1i njl02-d01v22lag cclpdael-82eerf-dael 5 25 15 10 3 1i npl52-d01v22lag pidcitsalpnip-42eerf-dael 03 1i njl52-d01v22lag cclpdael-82eerf-dael blank = commercial i = industrial grade package power l = low power q = quarter power speed (ns) xxxxxxxx xx x xx x device name _ p = plastic dip pn = lead-free plastic dip j = plcc jn = lead-free plcc s = soic gal22v10d all devices discontinued
specifications gal22v10 4 gal22v10 output logic macrocell (olmc) each of the macrocells of the gal22v10 has two primary functional modes: registered, and combinatorial i/o. the modes and the output polarity are set by two bits (so and s1), which are normally controlled by the logic compiler. each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. registered in registered mode the output pin associated with an individual olmc is driven by the q output of that olmc?s d-type flip-flop. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). output tri-state control is available as an in- dividual product-term for each olmc, and can therefore be defined by a logic equation. the d flip-flop?s /q output is fed back into the and array, with both the true and complement of the feedback available as inputs to the and array. note: in registered mode, the feedback is from the /q output of the register, and not from the pin; therefore, a pin defined as reg- istered is an output only, and cannot be used for dynamic i/o, as can the combinatorial pins. combinatorial i/o in combinatorial mode the pin associated with an individual olmc is driven by the output of the sum term gate. logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). out- put tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either ?on? (dedicated output), ?off? (dedicated input), or ?product-term driven? (dynamic i/o). feedback into the and array is from the pin side of the output enable buffer. both polarities (true and inverted) of the pin are fed back into the and array. the gal22v10 has a variable number of product terms per olmc. of the ten available olmcs, two olmcs have access to eight product terms (pins 14 and 23, dip pinout), two have ten product terms (pins 15 and 22), two have twelve product terms (pins 16 and 21), two have fourteen product terms (pins 17 and 20), and two olmcs have sixteen product terms (pins 18 and 19). in addition to the product terms available for logic, each olmc has an addi- tional product-term dedicated to output enable control. the output polarity of each olmc can be individually programmed to be true or inverting, in either combinatorial or registered mode. this allows each output to be individually configured as either active high or active low. the gal22v10 has a product term for asynchronous reset (ar) and a product term for synchronous preset (sp). these two prod- uct terms are common to all registered olmcs. the asynchronous reset sets all registers to zero any time this dedicated product term is asserted. the synchronous preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. note: the ar and sp product terms will force the q output of the flip-flop into the same state regardless of the polarity of the output. therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. ar sp d q q clk 4 to 1 mux 2 to 1 mux output logic macrocell (olmc) output logic macrocell configurations all devices discontinued
specifications gal22v10 5 active high active low active high active low s 0 = 1 s 1 = 1 s 0 = 0 s 1 = 1 s 0 = 0 s 1 = 0 s 0 = 1 s 1 = 0 ar sp d q q clk ar sp d q q clk registered mode combinatorial mode all devices discontinued
specifications gal22v10 6 dip (plcc) package pinouts 1 (2) 22 (26) olmc s0 5810 s1 5811 0440 . . . . 0880 2 (3) asynchronous reset (to all registers) 0 4 8 1216202428323640 synchronous preset (to all registers) 10 (12) 0000 5764 0044 . . . 0396 23 (27) s0 5808 s1 5809 21 (25) olmc s0 5812 s1 5813 0924 . . . . . 1452 3 (4) 4 (5) 5 (6) 20 (24) olmc s0 5814 s1 5815 1496 . . . . . . 2112 19 (23) olmc s0 5816 s1 5817 2156 . . . . . . . 2860 18 (21) olmc s0 5818 s1 5819 2904 . . . . . . . 3608 17 (20) olmc s0 5820 s1 5821 3652 . . . . . . 4268 olmc s0 5822 s1 5823 4312 . . . . . 4840 8 (10) 16 (19) 15 (18) olmc s0 5824 s1 5825 4884 . . . . 5324 9 (11) 5368 . . . 5720 14 (17) olmc s0 5826 s1 5827 7 (9) 6 (7) 11 (13) 13 (16) 8 10 14 16 12 12 16 14 10 8 olmc electronic signature 5828, 5829 ... ... 5890, 5891 l s b m s b byte 7 byte 6 byte 5 byte 4 byte 2 byte 1 byte 0 byte 3 gal22v10 logic diagram / jedec fuse map all devices discontinued
specifications gal22v10 7 supply voltage v cc ....................................... - 0.5 to +7v input voltage applied ........................... -2.5 to v cc +1.0v off-state output voltage applied ........... -2.5 to v cc +1.0v storage temperature .................................. -65 to 150 c ambient temperature with power applied ......................................... -55 to 125 c 1. stresses above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. these are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). commercial devices: ambient temperature (t a ) ............................. 0 to +75 c supply voltage (v cc ) with respect to ground ..................... +4.75 to +5.25v industrial devices: ambient temperature (t a ) ............................ -40 to 85 c supply voltage (v cc ) with respect to ground ..................... +4.50 to +5.50v specifications gal22v10d commercial i cc operating power v il = 0.5v v ih = 3.0v l-4/-5/-7 ? 90 140 ma supply current f toggle = 15mhz outputs open l-10 ? 90 130 ma l-15/-25 ? 75 90 ma q-10/-15/-25 ? 45 55 ma v il input low voltage vss ? 0.5 ? 0.8 v v ih input high voltage 2.0 ? vcc+1 v i il 1 input or i/o low leakage current 0v v in v il (max.) ? ? ?100 a i ih input or i/o high leakage current 3.5v v in v cc ??10 a v ol output low voltage i ol = max. vin = v il or v ih ? ? 0.4 v v oh output high voltage i oh = max. v in = v il or v ih 2.4 ? ? v i ol low level output current ? ? 16 ma i oh high level output current ? ? ?3.2 ma i os 2 output short circuit current v cc = 5v v out = 0.5v t a = 25 c ?30 ? ?130 ma over recommended operating conditions (unless otherwise specified) symbol parameter condition min. typ. 3 max. units industrial i cc operating power v il = 0.5v v ih = 3.0v l-7/-10 ? 90 160 ma supply current f toggle = 15mhz outputs open l-15/-20/-25 ? 75 130 ma 1) the leakage current is due to the internal pull-up on all pins. see input buffer section for more information. 2) one output at a time for a maximum duration of one second. vout = 0.5v was selected to avoid test problems caused by tester ground degradation. characterized but not 100% tested. 3) typical values are at vcc = 5v and t a = 25 c absolute maximum ratings 1 recommended operating conditions dc electrical characteristics all devices discontinued
specifications gal22v10 8 t pd a input or i/o to combinatorial output 1 4 1 5 1 7.5 ns t co a clock to output delay 1 3.5 1 4 1 4.5 ns t cf 2 ? clock to feedback delay ? 2.5 ? 3 ? 3 ns t su ? setup time, input or fdbk before clk 2.5 ? 3 ? 4.5 ? ns t h ? hold time, input or fdbk after clk 0 ?0?0?ns a maximum clock frequency with 167 ? 142.8 ? 111 ? mhz external feedback, 1/(tsu + tco) f max 3 a maximum clock frequency with 200 ? 166 ? 133 ? mhz internal feedback, 1/(tsu + tcf) a maximum clock frequency with 250 ? 200 ? 166 ? mhz no feedback t wh ? clock pulse duration, high 2 ? 2.5 ? 3 ? ns t wl ? clock pulse duration, low 2 ? 2.5 ? 3 ? ns t en b input or i/o to output enabled 1 5 1 6 1 7.5 ns t dis c input or i/o to output disabled 1 5 1 5.5 1 7.5 ns t ar a input or i/o to asynch. reset of reg. 1 4.5 1 5.5 1 9 ns t arw ? asynch. reset pulse duration 4.5 ? 4.5 ? 7 ? ns t arr ? asynch. reset to clk recovery time 3 ? 4 ? 5 ? ns t spr ? synch. preset to clk recovery time 3 ? 4 ? 5 ? ns over recommended operating conditions units 1) refer to switching test conditions section. 2) calculated from fmax with internal feedback. refer to fmax description section. 3) refer to fmax description section. characterized initially and after any design or process changes that may affect these parameters. param test cond. 1 description symbol parameter maximum* units test conditions c i input capacitance 8 pf v cc = 5.0v, v i = 2.0v c i/o i/o capacitance 8 pf v cc = 5.0v, v i/o = 2.0v *characterized but not 100% tested. -5 min. max. com/ind com -7 min. max. ac switching characteristics capacitance (t a = 25 c, f = 1.0 mhz) specifications gal22v10d com -4 min. max. all devices discontinued
specifications gal22v10 9 t pd a input or i/o to comb. output 1 10 3 15 3 20 3 25 ns t co a clock to output delay 1 7 2 8 2 10 2 15 ns t cf 2 ? clock to feedback delay ? 2.5 ? 2.5 ? 8 ? 13 ns t su ? setup time, input or fdbk before clk 6 ? 10 ? 12 ? 15 ? ns t h ? hold time, input or fdbk after clk 0? 0? 0 ? 0 ?ns a maximum clock frequency with 83.3 ? 55.5 ? 41.6 ? 33.3 ? mhz external feedback, 1/(tsu + tco) f max 3 a maximum clock frequency with 110 ? 80 ? 45.4 ? 35.7 ? mhz internal feedback, 1/(tsu + tcf) a maximum clock frequency with 125 ? 83.3 ? 50 ? 38.5 ? mhz no feedback t wh ? clock pulse duration, high 4 ? 6 ? 10 ? 13 ? ns t wl ? clock pulse duration, low 4 ? 6 ? 10 ? 13 ? ns t en b input or i/o to output enabled 1 10 3 15 3 20 3 25 ns t dis c input or i/o to output disabled 1 9 3 15 3 20 3 25 ns t ar a input or i/o to asynch. reset of reg. 1 13 3 20 3 25 3 25 ns t arw ? asynch. reset pulse duration 8 ? 15 ? 20 ? 25 ? ns t arr ? asynch. reset to clk recovery time 8 ? 10 ? 20 ? 25 ? ns t spr ? synch. preset to clk recovery time 8 ? 10 ? 14 ? 15 ? ns specifications gal22v10d -10 min. max. -25 min. max. -20 min. max. -15 min. max. over recommended operating conditions units 1) refer to switching test conditions section. 2) calculated from fmax with internal feedback. refer to fmax description section. 3) refer to fmax description section. symbol parameter maximum* units test conditions c i input capacitance 8 pf v cc = 5.0v, v i = 2.0v c i/o i/o capacitance 8 pf v cc = 5.0v, v i/o = 2.0v *characterized but not 100% tested. param. test cond. 1 description com / ind ind com / ind com / ind capacitance (t a = 25 c, f = 1.0 mhz) ac switching characteristics all devices discontinued
specifications gal22v10 10 input or i/o to output enable/disable registered output combinatorial output valid input input or i/o feedback t pd combinatorial output input or i/o feedback registered output clk valid input t su t co t h (external fdbk) 1/ f max t en t dis input or i/o feedback output clk (w/o fdbk) t wh t wl 1/ f max clock width registered output clk input or i/o feedback driving sp t su t h t co t spr registered output clk t arw t ar t arr input or i/o feedback driving ar f max with feedback asynchronous reset synchronous preset clk registered feedback t cf t su 1/ f max (internal fdbk) switching waveforms all devices discontinued
specifications gal22v10 11 f max with internal feedback 1/( t su+ t cf) note: f max with external feedback is cal- culated from measured tsu and tco. f max with external feedback 1/( t su+ t co) note: tcf is a calculated value, derived by sub- tracting tsu from the period of fmax w/internal feedback ( t cf = 1/ f max - t su). the value of t cf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. for example, the timing from clock to a combi- natorial output is equal to tcf + tpd. f max with no feedback note: f max with no feedback may be less than 1/( t wh + t wl). this is to allow for a clock duty cycle of other than 50%. register logic array t co t su clk register logic array clk t su + t h clk register logic array t cf t pd fmax descriptions all devices discontinued
specifications gal22v10 12 gal22v10d-4 output load conditions (see figure below) test condition r 1 c l a5 0 50pf b z to active high at 1.9v 50 50pf z to active low at 1.0v 50 50pf c active high to z at 1.9v 50 50pf active low to z at 1.0v 50 50pf input pulse levels gnd to 3.0v input rise and d-4/-5/-7 1.5ns 10% ? 90% fall times d-10/-15/-20/-25 2.0ns 10% ? 90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure 3-state levels are measured 0.5v from steady-state active level. test point c * l from output (o/q) under test +5v *c l includes test fixture and probe capacitance r 2 r 1 output load conditions (except d-4) (see figure below) test condition r 1 r 2 c l a 300 390 50pf b active high 390 50pf active low 300 390 50pf c active high 390 5pf active low 300 390 5pf test point z 0 = 50, c l * from output (o/q) under test +1.45v r 1 switching test conditions all devices discontinued
specifications gal22v10 13 electronic signature an electronic signature (es) is provided in every gal22v10 device. it contains 64 bits of reprogrammable memory that can contain user-defined data. some uses include user id codes, revision numbers, or inventory control. the signature data is always available to the user independent of the state of the se- curity cell. the electronic signature is an additional feature not present in other manufacturers' 22v10 devices. to use the extra feature of the user-programmable electronic signature it is necessary to choose a lattice semiconductor 22v10 device type when com- piling a set of logic equations. in addition, many device program- mers have two separate selections for the device, typically a gal22v10 and a gal22v10-ues (ues = user electronic sig- nature) or gal22v10-es. this allows users to maintain compat- ibility with existing 22v10 designs, while still having the option to use the gal device's extra feature. the jedec map for the gal22v10 contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. however, the gal22v10 device can still be programmed with a standard 22v10 jedec map (5828 fuses) with any qualified device pro- grammer. security cell a security cell is provided in every gal22v10 device to prevent unauthorized copying of the array patterns. once programmed, this cell prevents further read access to the functional bits in the device. this cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. the electronic signature is always avail- able to the user, regardless of the state of this control cell. latch-up protection gal22v10 devices are designed with an on-board charge pump to negatively bias the substrate. the negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pullups to eliminate any pos- sibility of scr induced latching. device programming gal devices are programmed using a lattice semiconductor- approved logic programmer, available from a number of manu- facturers (see the the gal development tools section). com- plete programming of the device takes only a few seconds. eras- ing of the device is transparent to the user, and is done automati- cally as part of the programming cycle. typical input current 1.0 2.0 3.0 4.0 5.0 -60 0 -20 -40 0 input voltage (volts) input current (ua) output register preload when testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. this is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). to test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. then the machine can be sequenced and the outputs tested for correct next state condi- tions. the gal22v10 device includes circuitry that allows each regis- tered output to be synchronously set either high or low. thus, any present state condition can be forced for test sequencing. if necessary, approved gal programmers capable of executing test vectors perform output register preload automatically. input buffers gal22v10 devices are designed with ttl level compatible in- put buffers. these buffers have a characteristically high imped- ance, and present a much lighter load to the driving logic than bi- polar ttl devices. the input and i/o pins also have built-in active pull-ups. as a re- sult, floating inputs will float to a ttl high (logic 1). however, lattice semiconductor recommends that all unused inputs and tri-stated i/o pins be connected to an adjacent active input, vcc, or ground. doing so will tend to improve noise immunity and reduce icc for the device. (see equivalent input and i/o schemat- ics on the following page.) all devices discontinued
specifications gal22v10 14 (vref typical = 3.2v) (vref typical = 3.2v) circuitry within the gal22v10 provides a reset signal to all reg- isters during power-up. all internal registers will have their q out- puts set low after a specified time (tpr, 1 s max). as a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. this feature can greatly simplify state machine design by providing a known state on power-up. the timing diagram for power-up is shown below. because of the asyn- chronous nature of system power-up, some conditions must be met to guarantee a valid power-up reset of the gal22v10. first, the vcc rise must be monotonic. second, the clock input must be at static ttl level as shown in the diagram during power up. the registers will reset within a maximum of tpr time. as in nor- mal system operation, avoid clocking the device until all input and feedback path setup times have been met. the clock must also meet the minimum pulse width requirements. vcc pin vcc vref active pull-up circuit esd protection circuit esd protection circuit vcc pin vcc (min.) t pr internal register reset to logic "0" device pin reset to logic "1" t wl t su device pin reset to logic "0" vcc clk internal register q - output active low output register active high output register vcc pin vref tri-state control active pull-up circuit feedback (to input buffer) pin feedback data output typical input typical output power-up reset input/output equivalent schematics all devices discontinued
specifications gal22v10 15 delta tpd vs # of outputs switching -0.3 -0.2 -0.1 0 12345678910 number of outputs switching delta tpd (ns) rise fall delta tco vs # of outputs switching -0.4 -0.3 -0.2 -0.1 0 12345678910 number of outputs switching delta tco (ns) delta tco (ns) rise fall delta tpd vs output loading output loading (pf) delta tpd (ns) rise fall delta tco vs output loading rise fall normalized tpd vs vcc normalized tpd normalized tpd rise fall normalized tco vs vcc rise fall normalized tsu vs vcc supply voltage (v) supply voltage (v) supply voltage (v) rise fall normalized tpd vs temp normalized tco vs temp normalized tsu vs temp 1251007550250-25-55 1251007550250-25-55 300 250 200 150 100 500 output loading (pf) 300 250 200 150 100 500 temperature (deg. c) temperature (deg. c) temperature (deg. c) 1251007550250-25-55 rise fall rise fall rise fall 5.5 5.25 5 4.75 4.5 0.9 1.3 1.2 1.1 1 0.9 0.8 12 8 4 0 -4 12 8 4 0 -4 1.3 1.2 1.1 1 0.9 0.8 0.9 1 1.1 1.2 0.95 1 1.05 1.1 normalized tco normalized tco 0.9 0.95 1 1.05 1.1 normalized t normalized t su 0.9 0.95 1 1.05 1.1 5.5 5.25 5 4.75 4.5 5.5 5.25 5 4.75 4.5 gal22v10d-4/-5/-7/-10l (plcc): typical ac and dc characteristic diagrams all devices discontinued
specifications gal22v10 16 vol vs iol 0 0.2 0.4 0.6 0 5 10 15 20 25 30 35 40 iol (ma) vol (v) voh vs ioh 0 1 2 3 4 0 5 10 15 20 25 30 35 40 45 50 55 60 ioh(ma) voh (v) voh vs ioh 3.15 3.25 3.35 3.45 3.55 3.65 3.75 3.85 3.95 0.00 1.00 2.00 3.00 4.00 5.00 ioh(ma) voh (v) normalized icc vs vcc 0.8 0.9 1 1.1 1.2 4.5 4.75 5 5.25 5.5 supply voltage (v) normalized icc normalized icc vs temp 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 88 100 125 temperature (deg. c) normalized icc normalized icc vs freq 0.95 1 1.05 1.1 1.15 1.2 1 15255075100 frequency (mhz) normalized icc input clamp (vik) vik (v) iik (ma) delta icc vs vin (1 input) 6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -3 100 80 60 40 20 0 -2.5 -2 -1.5 -1 -0.5 1 vin (v) delta icc (ma) gal22v10d-4/-5/-7/-10l (plcc): typical ac and dc characteristic diagrams all devices discontinued
specifications gal22v10 17 gal22v10d-7/10l (pdip): typical ac and dc characteristic diagrams normalized tpd vs vcc 0.9 0.95 1 1.05 1.1 4.5 4.75 5 5.25 5.5 supply voltage (v) normalized tpd rise fall normalized tco vs vcc 0.95 1 1.05 1.1 4.5 4.75 5 5.25 5.5 supply voltage (v) normalized tco rise fall normalized tsu vs vcc 0.8 0.9 1 1.1 1.2 4.5 4.75 5 5.25 5.5 supply voltage (v) normalized tsu rise fall normalized tpd vs temp 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 temperature (deg. c) normalized tpd rise fall normalized tsu vs temp 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 temperature (deg. c) normalized tsu rise fall normalized tco vs temp 0.8 0.9 1 1.1 1.2 -55 -25 0 25 50 75 100 125 temperature (deg. c) normalized tco rise fall delta tpd vs # of outputs switching -1.1 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 12345678910 number of outputs switching delta tpd (ns) rise fall delta tco vs # of outputs switching -1.1 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 12345678910 number of outputs switching delta tco (ns) rise fall delta tpd vs output loading -4 0 4 8 12 0 50 100 150 200 250 300 output loading (pf) delta tpd (ns) rise fall delta tco vs output loading -4 0 4 8 12 0 50 100 150 200 250 300 output loading (pf) delta tco (ns) rise fall all devices discontinued
specifications gal22v10 18 gal22v10d-7/10l (pdip): typical ac and dc characteristic diagrams vol vs iol 0 0.1 0.2 0.3 0.4 0.5 0 5 10 15 20 25 30 iol (ma) vol (v) voh vs ioh 0 1 2 3 4 0 5 10 15 20 25 30 35 40 ioh (ma) voh (v) voh vs ioh 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 0.00 1.00 2.00 3.00 4.00 5.00 ioh (ma) voh (v) normalized icc vs vcc 0.85 0.9 0.95 1 1.05 1.1 1.15 4.5 4.75 5 5.25 5.5 supply voltage (v) normalized icc normalized icc vs temp 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 0 25 100 temperature (deg. c) normalized icc normalized icc vs freq 0.95 1 1.05 1.1 1.15 1.2 1 15255075100 frequency (mhz) normalized icc input clamp (vik) 0 10 20 30 40 50 60 70 80 90 100 -2.5 -2 -1.5 -1 -0.5 0 vik (v) iik (ma) delta isb vs vin (1 input) 0 1 2 3 4 5 6 7 8 9 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 vin (v) delta icc (ma) all devices discontinued
specifications gal22v10 19 normalized tpd vs vcc 0.9 0.95 1 1.05 1.1 4.5 4.75 5 5.25 5.5 supply voltage (v) normalized tpd rise fall normalized tco vs vcc 0.9 0.95 1 1.05 1.1 1.15 4.5 4.75 5 5.25 5.5 supply voltage (v) normalized tco rise fall normalized tsu vs vcc 0.8 0.9 1 1.1 1.2 4.5 4.75 5 5.25 5.5 supply voltage (v) normalized tsu rise fall normalized tpd vs temp 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 temperature (deg. c) normalized tpd rise fall normalized tsu vs temp 0.75 0.85 0.95 1.05 1.15 1.25 1.35 1.45 -55 -25 0 25 50 75 100 125 temperature (deg. c) normalized tsu rise fall normalized tco vs temp 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 temperature (deg. c) normalized tco rise fall delta tpd vs # of outputs switching -1.2 -0.8 -0.4 0 12345678910 number of outputs switching delta tpd (ns) rise fall delta tco vs # of outputs switching -1.2 -0.8 -0.4 0 12345678910 number of outputs switching delta tco (ns) rise fall delta tpd vs output loading -8 -4 0 4 8 12 16 20 0 50 100 150 200 250 300 output loading (pf) delta tpd (ns) rise fall delta tco vs output loading -4 0 4 8 12 16 20 0 50 100 150 200 250 300 output loading (pf) delta tco (ns) rise fall gal22v10d-10q and slower (l & q): typical ac and dc characteristic diagrams all devices discontinued
specifications gal22v10 20 vol vs iol 0 0.2 0.4 0.6 0 5 10 15 20 25 30 35 40 iol (ma) vol (v) voh vs ioh 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 02 04 06 0 ioh (ma) voh (v) voh vs ioh 2.5 3 3.5 4 4.5 0.00 1.00 2.00 3.00 4.00 5.00 ioh (ma) voh (v) normalized icc vs vcc 0.8 0.9 1 1.1 1.2 4.5 4.75 5 5.25 5.5 supply voltage (v) normalized icc normalized icc vs temp 0.75 0.85 0.95 1.05 1.15 1.25 1.35 -55 -25 0 25 50 88 100 125 temperature (deg. c) normalized icc normalized icc vs freq 0.9 1 1.1 1.2 1.3 1.4 1 15255075100 frequency (mhz) normalized icc input clamp (vik) 0 10 20 30 40 50 60 70 80 90 -2.5 -2 -1.5 -1 -0.5 0 vik (v) iik (ma) delta icc vs vin (1 input) 0 1 2 3 4 5 6 7 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 vin (v) delta icc (ma) gal22v10d-10q and slower (l & q): typical ac and dc characteristic diagrams all devices discontinued
specifications gal22v10 21 notes revision history date version change summary - 22v10_08 previous lattice release. august 2004 22v10_09 added lead-free package options. july 2006 22v10_10 corrected soic pin configuration diagram. pin 13. august 2006 22v10_11 updated for lead-free package options. december 2006 22v10_12 corrected icc in the ordering part number section on pages 2-3. all devices discontinued

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